The present invention relates to a power detector used in a communication apparatus for transmitting and receiving high frequency signals, or a measurement device for measuring signal levels of high frequency signals, and a demodulator using the same.
In a conventional high frequency power detector, a Schottky barrier diode has often been mainly used.
FIG. 1 is circuit diagram of an example of the configuration of a conventional high frequency power detector using the diode.
As shown in FIG. 1, this high frequency power detector 1 is comprised of a diode D1 as an active element, a DC bias resistor R1, a capacitor C1, and a load resistor RL1.
An anode of the diode D1 is connected to an input terminal Tin1 of a high frequency signal RFin and one end of the resistor R1, while a cathode thereof is connected to an output terminal Tout1, one electrode of the capacitor C1 for removing a high frequency component, and one end of the load resistor RL1. The other ends of the resistors R1 and RL1 and the other electrode of the capacitor Cl are grounded.
In the high frequency power detector 1 having such a configuration, the high frequency signal RFin is input to the input terminal Tin1. By a rectification function of the diode D1 and the capacitor C1 having a sufficiently large capacitance, an envelope component of the input high frequency signal is output as a detection output signal Vout.
In the high frequency power detector 1, it is required to linearly obtain the detection output voltage Vout from a signal level as low as possible to a signal level as high as possible, that is in a wide dynamic range.
FIG. 2 is a diagram of an example of characteristics of the high frequency power detector using a diode as an active element.
This example plotted the relationship of the output voltage Vout with respect to an input high frequency power Pin obtained when a Schottky barrier diode was used, a bias voltage Vd of the diode D1 in FIG. 1 was set at 0V (Vd=0V: zero bias), and the frequency of the high frequency signal was 10 GHz.
The conventional power detector using a Schottky barrier diode having such a characteristic has the following disadvantages.
In order to raise the detection performance, the circuit is produced by using a special semiconductor process. Accordingly, the conventional power detector is not suited for an integrated circuit.
For this reason, the conventional power detector has to have a hybrid configuration. This induces a rise of production costs, a restriction of the operation band, and an increase of production variability.
When the power detector is comprised by a semiconductor process enabling circuit integration, the detection characteristic thereof is deteriorated.
In recent years, there have been strong demands for reduction of size and lowering of price of mobile phones and other wireless communications devices. Circuit integration is important as a means for responding to such demands.
Therefore, in order to obtain a high performance, high frequency power detector suited for circuit integration, a power detector using a field effect transistor (FET) as an active element has been investigated (for example, the above document).
FIG. 3 is a circuit diagram of an example of the configuration of a conventional high frequency power detector using a silicon (Si) MOSFET.
As shown in FIG. 3, this high frequency power detector 2 is comprised of a field effect transistor (hereinafter, simply referred to as a xe2x80x9ctransistorxe2x80x9d) Q1, resistors R2 and R3, capacitors C2 and C3, a voltage source V1, and a load resistor RL2.
In this high frequency power detector 2, a gate of the transistor Q1 is biased by a bias supply circuit comprised of the voltage source V1, resistor R3, and the capacitor C2. The input high frequency signal RFin is propagated through the transistor Q1 having a predetermined resistance between the drain and the source, and an envelope component of the input high frequency signal is output as the detection output signal Vout by the capacitor C3 having a large capacitance on the output side.
However, the high frequency power detector of FIG. 3 has the following disadvantages.
Since it uses an SiMOSFET, the maximum operation frequency is low, i.e., the 1.5 GHz band.
Also, as shown in FIG. 4, there is room for improvement of linearity of the input power versus detection output voltage characteristic (Mohamed RATNI, Bernard HUYART, et al., xe2x80x9cRF Power Detector using a Silicon MOSFETxe2x80x9d, International Microwave Symposium, 1998).
Also, in the power detector 2, where the output format is the single end system and the latter stage of the linear detector has a balance input, an additional unbalance/balance conversion circuit becomes necessary.
FIG. 5 is a circuit diagram of another example of the configuration of the high frequency power detector using a field effect transistor as an active element (refer to Japanese Unexamined Patent Publication (Kokai) No. 10-234474).
As shown in FIG. 5, this high frequency power detector 3 is comprised by a transistor (FET) Q2, a DC cutting capacitor Cin, a bias resistor R4, voltage sources V2 and V3, a load resistor RL3, an output side capacitor C4, a coupling capacitor Cd, and an inductor Ld. A gate bias supply circuit 3a is comprised by the resistor R4, while a drain bias supply circuit 3b is comprised by the inductor Ld.
In this high frequency power detector 3, the high frequency signal RFin input to an input terminal Tin3 is supplied via the DC cutting capacitor Cin to the gate of the transistor Q2. The gate of the transistor Q2 is supplied with the gate bias voltage of the gate bias supply circuit 3a connected to the voltage source V2 for supplying a voltage Vgg. Also, the drain of the transistor Q2 has connected to it the drain bias supply circuit 3b for supplying the drain bias voltage. Note that the voltage source V3 for supplying a DC voltage Vdd is connected to the drain bias supply circuit 3b. 
A coupling capacitor Cd having a sufficiently large capacitance value is connected between the drain of the transistor Q2 and a ground potential GND. The resistor RL3 and the coupling capacitor C4 having a sufficiently large capacitance value are connected in parallel between the source of the transistor Q2 and the ground potential GND. Then, a potential difference Vout between the transistor Q2 and the ground potential GND becomes the detection output signal.
FIG. 6 shows the detection characteristics of the high frequency power detector of FIG. 5.
This power detector 3 enables the realization of a detector of a small size and low cost and adapted to broadband high frequency operation, but has the following disadvantages.
As shown in FIG. 6, the fluctuation of the detection output voltage versus input power characteristic is large compared with the gate-source bias fluctuation.
As shown in FIG. 6, depending on the bias conditions, sometimes a DC offset occurs.
When a pinchoff voltage of the transistor Q2 fluctuates due to a production variability, temperature fluctuation, etc., the fluctuation of the detection output voltage versus input voltage characteristic is large.
Also, in the power detector 3, when the output format is the single end system and the latter stage of the linear detector has a balance input, an additional unbalance/balance conversion circuit becomes necessary.
The present invention was made in consideration of such a circumstance and has as an object thereof to provide a high performance power detector not only suited for monolithic structures, small in size, low in cost, and suited for broadband high frequency operation, but also excellent in the linearity of the detection characteristic relative to the bias fluctuation, having a small fluctuation of the detection characteristic relative to the FET threshold voltage fluctuation, having a small DC offset, and not requiring an a additional circuit even when the latter stage circuit has a balance input, and a demodulator using the same.
A first aspect of the present invention is a power detector for detecting a signal level of a high frequency signal, having a first field effect transistor having a gate supplied with the high frequency signal, a second field effect transistor having a source connected to a source of the first field effect transistor, a first gate bias supply circuit for supplying a gate bias voltage to the gate of the first field effect transistor, a second gate bias supply circuit for supplying a gate bias voltage to the gate of the second field effect transistor, a resistor connected between a connecting point of sources of the first field effect transistor and second field effect transistor and a reference potential, a drain bias supply circuit for supplying the drain bias voltage to drains of the first field effect transistor and second field effect transistor, a first capacitor connected between the drain of the first field effect transistor and a reference potential, and a second capacitor connected between the drain of the second field effect transistor and a reference potential, wherein a voltage difference between the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor is defined as the detection output.
A second aspect of the present invention is a power detector for detecting a signal level of a high frequency signal, having a first field effect transistor having a gate supplied with the high frequency signal, a second field effect transistor having a source connected to a source of the first field effect transistor, a first gate bias supply circuit for supplying a gate bias voltage to the gate of the first field effect transistor, a second gate bias supply circuit for supplying a gate bias voltage to a gate of the second field effect transistor, a third field effect transistor connected between the connecting point of sources of the first field effect transistor and second field effect transistor and a reference potential, a third gate bias supply circuit for supplying the gate bias voltage to the gate of the third field effect transistor, a drain bias supply circuit for supplying the drain bias voltage to drains of the first field effect transistor and second field effect transistor, a first capacitor connected between the drain of the first field effect transistor and a reference potential, and a second capacitor connected between the drain of the second field effect transistor and a reference potential, wherein the voltage difference between the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor is defined as the detection output.
A third aspect of the present invention is a power detector for detecting a signal level of a high frequency signal, having a first field effect transistor having a gate supplied with the high frequency signal, a second field effect transistor having a source connected to a source of the first field effect transistor, a first gate bias supply circuit for supplying a gate bias voltage to the gate of the first field effect transistor, a second gate bias supply circuit for supplying a gate bias voltage to the gate of the second field effect transistor, a first resistor and a second resistor connected in series between the connecting point of sources of the first field effect transistor and second field effect transistor and a reference potential and having the related connecting point supplied with the high frequency signal, an inductor connected between the connecting point of the first resistor and second resistor and a reference potential, a drain bias supply circuit for supplying the drain bias voltage to drains of the first field effect transistor and second field effect transistor, a first capacitor connected between the drain of the first field effect transistor and a reference potential, and a second capacitor connected between the drain of the second field effect transistor and the reference potential, wherein the voltage difference between the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor is defined as the detection output.
Preferably, the first field effect transistor and second field effect transistor have substantially identical characteristics, the drain bias supply circuit includes a first drain bias resistor connected between the drain of the first field effect transistor and the voltage source and a second drain bias resistor connected between the drain of the second field effect transistor and the voltage source, a resistance value of the first drain bias resistor and the resistance value of the second drain bias resistor are set at substantially equal values, and a capacitance value of the first capacitor and the capacitance value of the second capacitor are set. at substantially equal values.
Also, preferably, a ratio Wga/Wgb of a gate width Wga of the first field effect transistor and a gate width Wgb of the second field effect transistor is set to N, the drain bias supply circuit includes the first drain bias resistor connected between the drain of the first field effect transistor and the voltage source and the second drain bias resistor connected between the drain of the second field effect transistor and the voltage source, the first gate bias voltage of the first gate bias supply circuit and the second gate bias voltage of the second gate bias supply circuit are set to substantially equal, a resistance value Ra of the first drain bias resistor and a resistance value Rb of the second drain bias resistor are set so as to satisfy a condition of Ra/Rb=1/N, and the capacitance value of the first capacitor and the capacitance value of the second capacitor are set to substantially equal values.
A fourth aspect of the present invention is a power detector for detecting a signal level of a high frequency signal, having a first field effect transistor having a gate supplied with the high frequency signal and a source connected to a reference potential, a second field effect transistor having a source connected to a reference potential, a first gate bias supply circuit for supplying a gate bias voltage to the gate of the first field effect transistor, a second gate bias supply circuit for supplying a gate bias voltage to a gate of the second field effect transistor, a drain bias supply circuit for supplying a drain bias voltage to drains of the first field effect transistor and second field effect transistor, a first capacitor connected between the drain of the first field effect transistor and a reference potential, and a second capacitor connected between the drain of the second field effect transistor and a reference potential, wherein the voltage difference between the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor is defined as the detection output.
Preferably, the first field effect transistor and second field effect transistor have substantially identical characteristics, the drain bias supply circuit includes a first drain bias resistor connected between the drain of the first field effect transistor and the voltage source and a second drain bias resistor connected between the drain of the second field effect transistor and the voltage source, the first gate bias voltage of the first gate bias supply circuit and the gate bias voltage of the second gate bias supply circuit are substantially equal and set to a voltage substantially equal to the threshold voltage of the first and second field effect transistors, the resistance value of the first drain bias resistor and the resistance value of the second drain bias resistor are set at substantially equal values, and the capacitance value of the first capacitor and the capacitance value of the second capacitor are set at substantially equal values.
Also, preferably, the ratio Wga/Wgb of the gate width Wga of the first field effect transistor and the gate width Wgb of the second field effect transistor is set to N, the drain bias supply circuit includes the first drain bias resistor connected between the drain of the first field effect transistor and the voltage source and the second drain bias resistor connected between the drain of the second field effect transistor and the voltage source, the first gate bias voltage of the first gate bias supply circuit and the second gate bias voltage of the second gate bias supply circuit are set to voltages which are substantially equal to each other and substantially equal to the threshold voltage of the first and second field effect transistors, the resistance value Ra of the first drain bias resistor and the resistance value Rb of the second drain bias resistor are set so as to satisfy the condition of Ra/Rb=1/N, and the capacitance value of the first capacitor and the capacitance value of the second capacitor are set to substantially equal values.
Also, a demodulator according to a fifth aspect of the present invention has a first signal input terminal to which a first high frequency signal is input, a second signal input terminal to which a second high frequency signal is input, a generating means for generating two high frequency signals having a phase difference based on at least one high frequency signal between the first high frequency signal input from the first signal input terminal and the second high frequency signal input from the second signal input terminal and including at least one output terminal for outputting generated high frequency signals, at least one power detector for receiving as the input the high frequency signals output from the output terminal of the generating means and detecting the signal level of the input high frequency signals, and a conversion circuit for converting the output signal of the power detector to a plurality of signal components contained in the first or second high frequency signal, wherein the power detector has a first field effect transistor having a gate supplied with the high frequency signal, a second field effect transistor having a source connected to a source of the first field effect transistor, a first gate bias supply circuit for supplying a gate bias voltage to the gate of the first field effect transistor, a second gate bias supply circuit for supplying a gate bias voltage to a gate of the second field effect transistor, a resistor connected between the connecting point of sources of the first field effect transistor and second field effect transistor and a reference potential, a drain bias supply circuit for supplying a drain bias voltage to drains of the first field effect transistor and second field effect transistor, a first capacitor connected between the drain of the first field effect transistor and a reference potential, and a second capacitor connected between the drain of the second field effect transistor and a reference potential, wherein the voltage difference between the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor is defined as the detection output.
A demodulator according to a sixth aspect of the present invention has a first signal input terminal to which a first high frequency signal is input, a second signal input terminal to which a second high frequency signal is input, a generating means for generating two high frequency signals having a phase difference based on at least one high frequency signal between the first high frequency signal input from the first signal input terminal and the second high frequency signal input from the second signal input terminal and including at least one output terminal for outputting the generated high frequency signals, at least one power detector for receiving as input the high frequency signals output from the output terminal of the generating means and detecting the signal level of the input high frequency signals, and a conversion circuit for converting the output signal of the power detector to a plurality of signal components contained in the first or second high frequency signal, wherein the power detector has a first field effect transistor having a gate supplied with the high frequency signal, a second field effect transistor having a source connected to a source of the first field effect transistor, a first gate bias supply circuit for supplying a gate bias voltage to the gate of the first field effect transistor, a second gate bias supply circuit for supplying a gate bias voltage to the gate of the second field effect transistor, a third field effect transistor connected between the connecting point of sources of the first field effect transistor and second field effect transistor and a reference potential, a third gate bias supply circuit for supplying a gate bias voltage to a gate of the third field effect transistor, a drain bias supply circuit for supplying a drain bias voltage to drains of the first field effect transistor and second electric field effect transistor, a first capacitor connected between the drain of the first field effect transistor and a reference potential, and a second capacitor connected between the drain of the second field effect transistor and a reference potential, wherein the voltage difference between the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor is defined as the detection output.
A demodulator according to a seventh aspect of the present invention has a first signal input terminal to which a first high frequency signal is input, a second signal input terminal to which a second high frequency signal is input, a generating means for generating two high frequency signals having a phase difference based on at least one high frequency signal between the first high frequency signal input from the first signal input terminal and the second high frequency signal input from the second signal input terminal and including at least one output terminal for outputting generated high frequency signals, at least one power detector for receiving as input the high frequency signals output from the output terminal of the generating means and detecting the signal level of the input high frequency signals, and a conversion circuit for converting the output signal of the power detector to a plurality of signal components contained in the first or second high frequency signal, wherein the power detector has a first field effect transistor having a gate supplied with the high frequency signal, a second field effect transistor having a source connected to a source of the first field effect transistor, a first gate bias supply circuit for supplying a gate bias voltage to the gate of the first field effect transistor, a second gate bias supply circuit for supplying a gate bias voltage to a gate of the second field effect transistor, a first resistor and a second resistor connected in series between the connecting point of sources of the first field effect transistor and second field effect transistor and a reference potential and having the related connecting point supplied with the high frequency signal, an inductor connected between the connecting point of the first resistor and second resistor and the reference potential, a drain bias supply circuit for supplying a drain bias voltage to drains of the first field effect transistor and second field effect transistor, a first capacitor connected between the drain of the first field effect transistor and a reference potential, and a second capacitor connected between the drain of the second field effect transistor and a reference potential, wherein the voltage difference between the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor is defined as the detection output.
A demodulator according to an eighth aspect of the present invention has a first signal input terminal to which a first high frequency signal is input, a second signal input terminal to which a second high frequency signal is input, a generating means for generating two high frequency signals having a phase difference based on at least one high frequency signal between the first high frequency signal input from the first signal input terminal and the second high frequency signal input from the second signal input terminal and including at least one output terminal for outputting generated high frequency signals, at least one power detector for receiving as input the high frequency signals output from the output terminal of the generating means and detecting the signal level of the input high frequency signals, and a conversion circuit for converting the output signal of the power detector to a plurality of signal components contained in the first or second high frequency signal, wherein the power detector has a first field effect transistor having a gate supplied with the high frequency signal and a source connected to a reference potential, a second field effect transistor having a source connected to a reference potential, a first gate bias supply circuit for supplying a gate bias voltage to the gate of the first field effect transistor, a second gate bias supply circuit for supplying a gate bias voltage to a gate of the second field effect transistor, a drain bias supply circuit for supplying a drain bias voltage to drains of the first field effect transistor and second field effect transistor, a first capacitor connected between the drain of the first field effect transistor and a reference potential, and a second capacitor connected between the drain of the second field effect transistor and a reference potential, wherein the voltage difference between the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor is defined as the detection output.
According to the present invention, in the power detector, the first field effect transistor and the second field effect transistor are used as active elements.
The high frequency signal is supplied via for example a matching circuit or DC (direct current) cutting capacitor to the gate of the first field effect transistor.
Also, the gate of the first field effect transistor is supplied with a gate bias voltage of the first gate bias supply circuit. Similarly, the gate of the second field effect transistor is supplied with for example a gate bias voltage substantially equal to the first gate bias voltage of the second gate bias supply circuit.
Also, the drains of the first field effect transistor and second field effect transistor are supplied with drain bias voltages via for example resistors having substantially equal resistance values.
Between the drains of the first field effect transistor and the second field effect transistor and the reference potential (ground potential), first and second capacitors having sufficiently large capacitance values are connected, so the drains of the first field effect transistor and second field effect transistor exhibit a stable state in terms of high frequency, and the voltage difference between the voltage of the drain of the first field effect transistor and the voltage of the drain of the second field effect transistor is supplied as the detection output signal to for example the conversion circuit of the latter stage.